One or more aspects relate generally to the field of processing units. More specifically, one or more aspects relate to a processing unit including a master storage entity and multiple shadow storage entities, in which the processing unit performs an update routine for updating the shadow storage entities.
In processing units, for example in central processing units (CPUs) of computer systems, a processor subsystem with a CPU-core may hold a master copy of all registers representing the complete architecture state of this CPU-core. The state may be used for recovering the system state (checkpoint restart) after an error has occurred. The architecture state may be updated with every instruction execution of this CPU-core, i.e. according to a first clock cycle time at which the core is operated.
The functional logic of the processing unit may not work directly with the master copy of these registers, but may use local shadow storage entities distributed throughout the CPU-core which can be accessed and updated with lower latency than the master copy. A result bus is distributed throughout the CPU-core in different staging levels, providing updates to all shadow copies at active edges of the first clock cycle.
In typical environments, not all shadow storage entities are actually operating at the first clock cycle. Typically, some of them are associated with subunits running at a slower cycle time than the first clock cycle, which makes it desirable, to operate also these shadow storage entities at a slower cycle time. This, however, causes problems with missing updates from the result bus, since those updates can only be captured by the slower clocked shadow storage entity, if they coincide with the active clock edge at which the shadow storage entity is operating. When updates occur randomly every core cycle, then this coincidence statistically exists only for one out of N updates, i.e. the delivery of the updates to the shadow storage entities cannot be guaranteed.
Other state of the art implementations run the shadow storage entities at core speed, i.e. at first clock cycle time, although actually being used in a slower domain, which is bad for timing and power.